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Hardik Shah

Hardik Shah

M.S. (TH) Electrical Engineering

fortiss GmbH
Guerickestr. 25
80805 München

Phone: +49 (0)89 360352215
E-Mail: shah@fortiss.org
Web: www.fortiss.org

Curriculum Vitae

  • 1999-2003: Bachelor of Engineering in Electronics & Communication; C.K.P.C.E.T. India
  • 2004-2006: Master of Science in Electrical Engineering; KTH-Royal Institute of Technology, Stockholm, Sweden
  • 2006-2008: Digital Hardware Engineer; Nero AG, Karlsbad, Germany
  • 2008-2009: Hardware Engineer; TES Electronic Solutions, Düsseldorf, Germany
  • since 2010: Research Assistant in Cyber-Physical Systems group at fortiss

Publications

2012

  • Hardik Shah, Andreas Raabe and Alois Knoll. Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs. In Design, Automation and Test in Europe (DATE). Dresden, Germany, March 2012.

2011

  • Hardik Shah, Andreas Raabe and Alois Knoll. Priority division: A high-speed shared-memory bus arbitration with bounded latency. In Design, Automation and Test in Europe (DATE). Grenoble, France. March 2011.

fortiss GmbH - An-Institut der Technischen Universität München

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